View ISL28470_711357.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

(R)
ISL28270, ISL28273, ISL28470
Data Sheet April 13, 2007 FN6260.2
Micropower, Single Supply, Rail-to-Rail Input and Output (RRIO) Instrumentation Amplifier
The ISL28270 and ISL28273 are dual channel micropower instrumentation amplifiers (in-amps) and the ISL28470 is a Quad-channel in-amp optimized for low 2.4V to 5V single supplies. All three devices feature an Input Range Enhancement Circuit (IREC) which maintains CMRR performance for input voltages equal to the positive supply and down to 50mV above the negative supply rail. The input signal is capable of swinging above the positive supply rail and to 10mV above the negative supply with only a slight degradation of the CMRR performance. The output operation is rail to rail. The ISL28273 is compensated for a minimum gain of 10 or more. For higher gain applications, the ISL28270 and ISL28470 are compensated for a minimum gain of 100. The in-amps have bipolar input devices for best offset and excellent 1/f noise performance. The amplifiers can be operated from one lithium cell or two Ni-Cd batteries.
Features
* 60A supply current per channel ISL28270 * 150V max offset voltage * 2nA max input bias current ISL28270 * 110dB CMRR, PSRR * 0.7V/C offset voltage temperature coefficient * 240kHz -3dB bandwidth (G = 100) ISL28270, ISL28470 * 230kHz -3dB bandwidth (G = 10) ISL28273 * 0.5V/s slew rate * Single supply operation * Rail-to-rail input and output (RRIO) * Input is capable of swinging above V+ and below V(ground sensing) * Output sources and sinks 29mA load current * 0.5% gain error * Pb-free plus anneal available (RoHS compliant)
Ordering Information
PART NUMBER (Note) ISL28270IAZ (Note) ISL28270IAZ-T13 (Note) Coming Soon ISL28273FAZ (Note) Coming Soon ISL28273FAZ-T7 (Note) ISL28470FAZ (Note) ISL28470FAZ-T7 (Note) PART MARKING 28270 IAZ 28270 IAZ 28273 FAZ TAPE & REEL PACKAGE (Pb-Free) PKG. DWG. #
Applications
* Battery or solar-powered systems * Strain gauge * Sensor signal conditioning * Medical devices * Industrial instrumentations
97/Tube 16 Ld QSOP MDP0040 (Pb-free) 13" 16 Ld QSOP MDP0040 (1k pcs) (Pb-free) 97/Tube 16 Ld QSOP MDP0040 (Pb-free) 7" 16 Ld QSOP MDP0040 (1k pcs) (Pb-free) 48/Tube 28 Ld QSOP M28.15 (Pb-free) 7" 28 Ld QSOP M28.15 (1k pcs) (Pb-free)
Related Literature
* AN1290, ISL2827xINEVAL1Z Evaluation Board User's Guide * AN1298, Instrumentation Amplifier Application Note
28273 FAZ
ISL28470FAZ ISL28470FAZ
ISL28270INEVAL1Z Evaluation Platform (Note) ISL28273INEVAL1Z Evaluation Platform Coming Soon ISL28470EVAL1Z Evaluation Platform
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2006, 2007. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
ISL28270, ISL28273, ISL28470 Pinouts
ISL28270, ISL28273 (16 LD QSOP) TOP VIEW
NC 1 OUT_A 2 FB+_A 3 FB-_A 4 IN-_A 5 IN+_A 6 EN_A 7 V- 8 +-+ 16 V+ 15 OUT_B 14 FB+_B 13 FB-_B 12 IN-_B 11 IN+_B 10 EN_B 9 NC OUT_A 1 FB+_A 2 FB-_A 3 IN-_A 4 IN+_A 5 EN_A 6 V- 7 EN_B 8 IN+_B 9 IN-_B 10 FB-_B 11 FB+_B 12 OUT_B 13 NC 14 +-+ +-+
ISL28470 (28 LD QSOP) TOP VIEW
28 OUT_D 27 FB+_D 26 FB-_D 25 IN-_D 24 IN+_D 23 EN_D 22 V21 EN_C 20 IN+_C 19 IN-_C 18 FB-_C 17 FB+_C 16 OUT_C 15 NC
2
FN6260.2 April 13, 2007
ISL28270, ISL28273, ISL28470
Absolute Maximum Ratings (TA = +25C)
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V Supply Turn On Voltage Slew Rate . . . . . . . . . . . . . . . . . . . . . 1V/s Input Current (IN, FB) ISL28270, ISL28470 . . . . . . . . . . . . . . . 5mA Differential Input Voltage (IN, FB) ISL28270, ISL28470 . . . . . . 0.5V Input Current (IN, FB) ISL28273 . . . . . . . . . . . . . . . . . . . . . . . . 5mA Differential Input (IN, FB) Voltage ISL28273 . . . . . . . . . . . . . . . 1.0V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . V- - 0.5V to V+ + 0.5V ESD Tolerance Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V
Thermal Information
Thermal Resistance JA (C/W) 16 Ld QSOP Package . . . . . . . . . . . . . . . . . . . . . . . 112 28 Ld QSOP Package . . . . . . . . . . . . . . . . . . . . . . . 79 Output Short-Circuit Duration . . . . . . . . . . . . . . . . . . . . . . .Indefinite Ambient Operating Temperature Range . . . . . . . . .-40C to +125C Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . +125C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER VOS
V+ = +5V, VM = GND, VCM = 1/2V+, TA = +25C, unless otherwise specified. Boldface limits apply over the operating temperature range, -40C to +125C. CONDITIONS ISL28270, ISL28470 ISL28273 MIN -150 -225 TYP
35
DESCRIPTION Input Offset Voltage
MAX 150 225
UNIT V V V/C
TBD 0.7 -1 -1.5 -1.5 -2.0
0.25
TCVOS IOS
Input Offset Voltage Temperature Coefficient Input Offset Current between IN+ and IN-, and between FB+ and FB-
Temperature = -40C to +125C ISL28270
1 1.5 1.5 2
nA
ISL28470 ISL28273 IB Input Bias Current (IN+, IN-, FB+, and FB- terminals) ISL28270
0.25
nA nA
TBD -2.0 -2.5 -2.5 -3.0
0.5
2.0 2.5 2.5 3.0
nA
ISL28470
0.5
nA
ISL28273 eN Input Noise Voltage ISL28270, ISL28470 ISL28273 Input Noise Voltage Density ISL28270, ISL28470 ISL28273 iN Input Noise Current Density ISL28270, ISL28470 ISL28273 RIN Input Resistance ISL28270, ISL28470 ISL28273 VIN Input Voltage Range V+ = 2.4V to 5.0V 0 fo = 1kHz fo = 1kHz f = 0.1Hz to 10Hz
TBD 3.5 3.5 60 210 0.48 0.65 3 15 V+
nA VP-P VP-P nV/Hz nV/Hz pA/Hz pA/Hz M M V
3
FN6260.2 April 13, 2007
ISL28270, ISL28273, ISL28470
Electrical Specifications
PARAMETER CMRR V+ = +5V, VM = GND, VCM = 1/2V+, TA = +25C, unless otherwise specified. Boldface limits apply over the operating temperature range, -40C to +125C. (Continued) CONDITIONS ISL28270 ISL28273 ISL28470 PSRR Power Supply Rejection Ratio ISL28270 ISL28273 ISL28470 EG Gain Error ISL28270, ISL28470 ISL28273 VOUT Maximum Voltage Swing Output low, 100k to 2.5V Output low, 1k to 2.5V Output high, 100k to 2.5V Output high, 1k to GND SR -3dB BW Slew Rate -3dB Bandwidth RL = 1k to GND ISL28270, ISL28470 Gain = 100 Gain = 200 Gain = 500 Gain = 1000 ISL28273 Gain = 10 Gain = 20 Gain = 50 Gain = 100 IS,EN Supply Current, Enabled ISL28270 - Both A and B channels enabled, EN = VISL28470 - A, B, C and D channels enabled, EN = VIS,DIS Supply Current, Disabled ISL28270 - Both A and B channels disabled, EN = V+ ISL28470 - A, B, C and D channels disabled, EN = V+ VENH VENL IENH IENL V+ EN Pin for Shut-down EN Pin for Power-On EN Input Current High EN Input Current Low Minimum Supply Voltage EN = V+ EN = V2.4 0.8 26 2 0.8 1 1.3 50 100 4.990 4.75 4.70 0.3 0.25 RL = 100k to 2.5V 90 65 V+ = 2.4V to 5V 90 85 90 TBD VCM = 0.05V to 5V MIN 90 TBD TYP 110 TBD 110 110 TBD 110 +0.5 TBD 4 130 4.996 4.88 0.5 240 84 30 13 265 100 25 13 120 260 4 10 156 195 335 7 9 12 15 0.7 0.75 10 250 300 MAX UNIT dB dB dB dB dB dB % % mV mV V V V/s kHz kHz kHz kHz kHz kHz kHz kHz A A A A V V A nA V
DESCRIPTION Common Mode Rejection Ratio
4
FN6260.2 April 13, 2007
ISL28270, ISL28273, ISL28470
Electrical Specifications
PARAMETER ISC V+ = +5V, VM = GND, VCM = 1/2V+, TA = +25C, unless otherwise specified. Boldface limits apply over the operating temperature range, -40C to +125C. (Continued) CONDITIONS V+ = 5V, RLOAD = 10 V+ = 2.4V, RLOAD = 10 MIN 20 18 TYP 29 8 MAX UNIT mA mA
DESCRIPTION Short Circuit Output Current
Typical Performance Curves
90 80 70 60 50 40 30 1 10 100 1k 10k FREQUENCY (Hz) 100k 1M GAIN = 2,000V/V GAIN = 1,000V/V GAIN = 500V/V GAIN = 200V/V GAIN = 100V/V COMMON-MODE INPUT = VS+ GAIN = 10,000V/V GAIN = 5,000V/V 50 GAIN (dB) 40 30 20 10 1E+00 GAIN (dB) 70 60 GAIN = 1000 GAIN = 500 GAIN = 200 GAIN = 100 GAIN = 50 GAIN = 20 GAIN = 10 1E+01 1E+02 1E+03 1E+04 1E+05 1E+06 COMMON-MODE INPUT = V+
FREQUENCY (Hz)
FIGURE 1. ISL28270, ISL28470 FREQUENCY RESPONSE vs CLOSED LOOP GAIN (V+ = VCM = 5V)
FIGURE 2. ISL28273 FREQUENCY RESPONSE vs CLOSED LOOP GAIN (VCM = V+)
90 80 70 GAIN (dB) 60 50 40 30 GAIN = 2,000V/V GAIN = 1,000V/V GAIN = 500V/V GAIN = 200V/V GAIN = 100V/V
COMMON-MODE INPUT = 1/2VS GAIN = 10,000V/V GAIN = 5,000V/V
70 60 50 GAIN (dB) 40 30 20 GAIN = 1000 GAIN = 500 GAIN = 200 GAIN = 100 GAIN = 50 GAIN = 20 GAIN = 10
COMMON-MODE INPUT = 1/2V+
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
10 1E+00
1E+01
1E+02 1E+03 1E+04 FREQUENCY (Hz)
1E+05
1E+06
FIGURE 3. ISL28270, ISL28470 FREQUENCY RESPONSE vs CLOSED LOOP GAIN (V+ = 5V, VCM = 1/2V+)
FIGURE 4. ISL28273 FREQUENCY RESPONSE vs CLOSED LOOP GAIN (VCM = 1/2V+)
5
FN6260.2 April 13, 2007
ISL28270, ISL28273, ISL28470 Typical Performance Curves (Continued)
90 80 70 GAIN (dB) 60 GAIN = 500V/V 50 40 30 GAIN = 200V/V GAIN = 100V/V COMMON-MODE INPUT = VM +10mV GAIN = 10,000V/V GAIN = 5,000V/V GAIN = 2,000V/V GAIN = 1,000V/V GAIN (dB) 50 40 30 20 10 1E+00 70 60 COMMON-MODE INPUT = VM +10mV GAIN = 1000 GAIN = 500 GAIN = 200 GAIN = 100 GAIN = 50 GAIN = 20 GAIN = 10
1
10
100 1k 10k FREQUENCY (Hz)
100k
1M
1E+01
1E+02 1E+03 1E+04 FREQUENCY (Hz)
1E+05
1E+06
FIGURE 5. ISL28270, ISL28470 FREQUENCY RESPONSE vs CLOSED LOOP GAIN (V+ = 5V, VCM = 10mV)
FIGURE 6. ISL28273 FREQUENCY RESPONSE vs CLOSED LOOP GAIN (VCM = V-)
45 40 35 GAIN (dB) 30 GAIN (dB) 25 20 15 10 5 AV = 100 RL = 10k CL = 10pF RF/RG = 99.02 RF = 221k RG = 2.23k 1k 10k 100k 1M FREQUENCY (Hz) VS = 3.3V VS = 5V
25 V+ = 5V 20 V+ = 3.3V 15 V+ = 2.4V AV = 10 R = 10k CL = 10pF RF/RG = 9.08 RF = 178k RG = 19.6k 1k 10k FREQUENCY (Hz) 100k 1M
VS = 2.4V
10
5
0 100
0 100
FIGURE 7. ISL28270, ISL28470 FREQUENCY RESPONSE vs SUPPLY VOLTAGE
FIGURE 8. ISL28273 FREQUENCY RESPONSE vs SUPPLY VOLTAGE
50
30 25 CL = 470pF CL = 820pF 20 GAIN (dB) CL = 27pF 15 CL = 2.7pF 10 5 AV = 10 V+ = 5V RL = 10k RF/RG = 9.08 RF = 178k RG = 19.6k 1k 10k FREQUENCY (Hz) 100k 1M CL = 47pF CL = 100pF
45
GAIN (dB)
40 CL = 220pF 35 AV = 100 VS = 2.5V RL = 10k RF/RG = 99.02 RF = 221k RG = 2.23k 1k 10k FREQUENCY (Hz) CL = 56pF
30
25 100
100k
1M
0 100
FIGURE 9. ISL28270, ISL28470 FREQUENCY RESPONSE vs CLOAD
FIGURE 10. ISL28273 FREQUENCY RESPONSE vs CLOAD
6
FN6260.2 April 13, 2007
ISL28270, ISL28273, ISL28470 Typical Performance Curves (Continued)
120 100 80 CMRR (dB) 60 40 20 0 10 CMRR 90 80 70 60 50 40 30 20 10 0 100 1k 10k 100k 1M -10 10 100 1k 10k 100k 1M CMRR
CMRR (dB)
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 11. ISL28270, ISL28470 CMRR vs FREQUENCY
FIGURE 12. ISL28273 CMRR vs FREQUENCY
140 120 100 80 60 40 20 0 10 100 1k 10k FREQUENCY (Hz) 100k 1M PSRRPSRR+ PSRR (dB)
90 80 70 60 50 40 30 20 10 0 10 100 1k 10k FREQUENCY (Hz) 100k 1M PSRRPSRR+
PSRR (dB)
FIGURE 13. ISL28270, ISL28470 PSRR vs FREQUENCY
FIGURE 14. ISL28273 PSRR vs FREQUENCY
250 INPUT VOLTAGE NOISE (nV/Hz) INPUT VOLTAGE NOISE (V/Hz)
2.5 2.0 1.5 1.0 0.5 0.0
200
150
100
50
1
10
100
1k
10k
100k
1
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 15. ISL28270, ISL28470 INPUT VOLTAGE NOISE SPECTRAL DENSITY (GAIN = 100)
FIGURE 16. ISL28273 INPUT VOLTAGE NOISE SPECTRAL DENSITY (GAIN = 10)
7
FN6260.2 April 13, 2007
ISL28270, ISL28273, ISL28470 Typical Performance Curves (Continued)
1.0 CURRENT NOISE (pA/Hz) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 1 10 100 1k 10k 100k CURRENT NOISE (pA/Hz) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 1 10 100 1k 10k 100k
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 17. ISL28270, ISL28470 INPUT CURRENT NOISE SPECTRAL DENSITY (GAIN = 100)
FIGURE 18. ISL28273 INPUT CURRENT NOISE SPECTRAL DENSITY (GAIN = 10)
VOLTAGE NOISE (0.5V/DIV)
VOLTAGE NOISE (0.5V/DIV)
TIME (1s/DIV)
TIME (1s/DIV)
FIGURE 19. ISL28270, ISL28470 0.1 Hz TO 10Hz INPUT VOLTAGE NOISE (GAIN = 100)
FIGURE 20. ISL28273 0.1 Hz TO 10Hz INPUT VOLTAGE NOISE (GAIN = 10)
400 n = 930 350 MAX CURRENT (A) 300 CMRR (dB) 250 200 150 MIN MIN 100 -40 -20 0 20 40 60 80 100 120 MEDIAN
140 135 130 125 120 115 110 105 100 95 90 -40 -20 0 20 40 60 80 100 120 MEDIAN MIN n = 930 MAX
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 21. SUPPLY CURRENT vs TEMPERATURE VS = 2.5V ENABLED (RL = INF)
FIGURE 22. CMRR vs TEMPERATURE (VCM = +2.5V TO -2.5V)
8
FN6260.2 April 13, 2007
ISL28270, ISL28273, ISL28470 Typical Performance Curves (Continued)
165 155 145 135 PSRR (dB) 125 115 105 95 85 75 65 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (C) MIN 4.85 -40 -20 0 20 40 4.86 MIN MEDIAN
OU
4.90 n = 930 n = 930 MAX 4.89 MAX
VOUT (V)
4.88
4.87
MEDIAN
60
80
100
120
TEMPERATURE (C)
FIGURE 23. PSRR vs TEMPERATURE (VS = 2.5V)
FIGURE 24. POSITIVE VOUT vs TEMPERATURE (RL = 1k, VS = 2.5V)
170 n = 930 160 150 VOUT (mV) 140 130 120 110 100 -40 -20 0 20 40 60 80 TEMPERATURE (C) 100 120 MIN MEDIAN MAX VOUT (V)
4.9964 4.9962 4.9960 4.9958 4.9956 4.9954 4.9952 4.9950 4.9948 4.9946 4.9944 -40
n = 930
MAX
MEDIAN
MIN -20 0 20 40 60 80 100 120
TEMPERATURE (C)
FIGURE 25. NEGATIVE VOUT vs TEMPERATURE (RL = 1k, VS = 2.5V)
FIGURE 26. POSITIVE VOUT vs TEMPERATURE (RL = 100k, VS = 2.5V)
4.502 n = 930 4.002 MEDIAN VOUT (mV) 3.502 MAX
3.002
MIN
2.502
2.002 -40
-20
0
20
40
60
80
100
120
TEMPERATURE (C)
FIGURE 27. NEGATIVE VOUT vs TEMPERATURE (RL = 100k, VS = 2.5V)
9
FN6260.2 April 13, 2007
ISL28270, ISL28273, ISL28470 Pin Descriptions
ISL28270 ISL28273 ISL28470 16 Ld QSOP 16 Ld QSOP 28 Ld QSOP 2, 15 2, 15 1, 13 16, 28 2, 12 17, 27 PIN NAME OUT_A,B C_D FB+_A,B C_D EQUIVALENT CIRCUIT Circuit 3 PIN FUNCTION Output Voltage. A complementary Class AB common-source output stage drives the output of each channel. When disabled, the outputs are in a high impedance state Positive Feedback high impedance terminals. ISL28270 and ISL28470 input circuit is shown in Circuit 1A, and the ISL28273 input circuit is shown in Circuit 1B. ISL28273: to avoid offset drift, it is recommended that the terminals of the ISL28273 are not overdriven beyond 1V and the input current must never exceed 5mA. 4, 13 4, 13 3, 11 18, 26 FB-_A,B C_D Circuit 1A, Circuit 1B Negative Feedback high impedance terminals. The FB- pins connect to an external resistor divider to individually set the desired gain of the inamp. ISL28270 and ISL28470 input circuit is shown in Circuit 1A, and the ISL28273 input circuit is shown in Circuit 1B. ISL28273: to avoid offset drift, it is recommended that the terminals of the ISL28273 are not overdriven beyond 1V and the input current must never exceed 5mA. 5, 12 5, 12 4, 10 19, 25 IN-_A,B C_D Circuit 1A, Circuit 1B High impedance Inverting input terminals. Connect to the low side of the input source signal. ISL28270 and ISL28470 input circuit is shown in Circuit 1A, and the ISL28273 input circuit is shown in Circuit 1B. ISL28273: to avoid offset drift, it is recommended that the terminals of the ISL28273 are not overdriven beyond 1V and the input current must never exceed 5mA. 6, 11 6, 11 5, 9 20, 24 IN+_A,B C_D Circuit 1A, Circuit 1B High impedance Non-inverting input terminals. Connect to the high side of the input source signal. ISL28270 and ISL28470 input circuit is shown in Circuit 1A, and the ISL28273 input circuit is shown in Circuit 1B. ISL28273: to avoid offset drift, it is recommended that the terminals of the ISL28273 are not overdriven beyond 1V and the input current must never exceed 5mA. 7, 10 7, 10 6, 8 21, 23 EN_A,B C_D Circuit 2 Active LOW logic pins. When pulled above 2V, the corresponding channel turns off and OUT is high impedance. A channel is enabled when pulled below 0.8V. Built-in pull downs define each EN pin LOW when left floating. Positive Supply terminal shared by all channels. Negative Supply terminal shared by all channels. Grounded for single supply operation. No Connect, pins can be left floating or grounded
V+ V+ LOGIC PIN VCIRCUIT 2 V+ INFBIN+ FB+ VCIRCUIT 3 OUT VVCIRCUIT 4
3, 14
3, 14
Circuit 1A, Circuit 1B
16 8 1, 9
16 8 1, 9
7 22 14,15
V+ VNC
Circuit 4 Circuit 4
V+ INFBIN+ FB+ V-
V+ CAPACITIVELY COUPLED ESD CLAMP
CIRCUIT 1A
CIRCUIT 1B
10
FN6260.2 April 13, 2007
ISL28270, ISL28273, ISL28470 Application Information
Product Description
The ISL28270 and ISL28273 are dual channel micropower instrumentation amplifiers (in-amps) and the ISL28470 is a Quad-channel which delivers rail-to-rail input amplification and rail-to-rail output swing. The in-amps also deliver excellent DC and AC specifications while consuming only about 60A per channel. Because the independent pair of feedback terminals set the gain and adjust the output 0 level, the ISL28270, ISL28273 and ISL28470 achieve high CMRR regardless of the tolerance of the gain setting resistors. The ISL28270 and ISL28470 are internally compensated for a minimum gain of 100. The ISL28273 is internally compensated for a minimum gain of 10. EN pins are available to independently enable or disable a channel. When all channels are off, current consumption is down to typically 4A. The IREC enables rail-to-rail input amplification without the problems usually associated with the dual differential stage topology. The IREC ensures that there are no drastic changes in offset voltage over the entire range of the input. See Input Offset Voltage vs Common-Mode Input Voltage in performance charts. IREC also cures the abrupt change and even reverse polarity of the input bias current over the whole range of input.
Input Bias Cancellation/Compensation
All three parts have an Input Bias Cancellation/Compensation Circuit for both the input and feedback terminals (IN+, IN-, FB+ and FB-), achieving a low input bias current throughout the input common-mode range and the operating temperature range. While the PNP bipolar input stages are biased with an adequate amount of biasing current for speed and increased noise performance, the Input Bias Cancellation/Compensation Circuit sinks most of the base current of the input transistors leaving a small portion as input bias current, typically 500pA. In addition, the Input Bias Cancellation/Compensation Circuit maintains a smooth and flat behavior of input bias current over the common mode range and over the operating temperature range. The Input Bias Cancellation/Compensation Circuit operates from input voltages of 10mV above the negative supply to input voltages slightly above the positive supply.
Input Protection
All input terminals and feedback terminals have internal ESD protection diodes to both positive and negative supply rails, limiting the input voltage to within one diode beyond the supply rails. Input signals originating from low impedance sources should have current limiting resistors in series with the IN+ and IN- pins to prevent damaging currents during power supply sequencing and other transient conditions. The ISL28270 and ISL28470 have additional back-to-back diodes across the input terminals and also across the feedback terminals. If overdriving the inputs is necessary, the external input current must never exceed 5mA. External series resistors may be used as an external protection to limit excessive external voltage and current from damaging the inputs. On the other hand, the ISL28273 has no clamps to limit the differential voltage on the input terminals allowing higher differential input voltages at lower gain applications. It is recommended, however, that the terminals of the ISL28273 are not overdriven beyond 1V to avoid offset drift.
Output Stage and Output Voltage Range
A Class AB common-source output stage drives the output. The pair of complementary MOSFET devices drive the output VOUT to within a few millivolts of the supply rails. At a 100k load, the PMOS sources current and pulls the output up to 4mV below the positive supply. The NMOS sinks current and pulls the output down to 4mV above the negative supply, or ground in the case of a single supply operation. The current sinking and sourcing capability are internally limited to 29mA. When disabled, the outputs are in a high impedance state.
Gain Setting
VIN (the potential difference across IN+ and IN-), is replicated (less the input offset voltage) across FB+ and FB-. The function of the in-amp is to maintain the differential voltage across FB- and FB+ equal to IN+ and IN-; (FB- FB+) = (IN+ - IN-). Consequently, the transfer function can be derived. The in-amp gain is set by two external resistors, the feedback resistor RF, and the gain resistor RG.
Input Stage and Input Voltage Range
The input terminals (IN+ and IN-) of the in-amps are a single differential pair of bipolar PNP devices aided by an Input Range Enhancement Circuit (IREC), to increase the headroom of operation of the common-mode input voltage. The feedback terminals (FB+ and FB-) also have a similar topology. As a result, the input common-mode voltage range is rail-to-rail regardless of the feedback terminal settings and regardless of the gain settings. They are able to handle input voltages that are at or slightly beyond the supply and close to ground making these in-amps well suited for single 5V down to 2.4V supply systems. There is no need to bias the common-mode input to achieve symmetrical input voltage. It is recommended, however, that the common-mode input be biased at least 10mV above the negative supply rail to achieve top performance. See "Input Bias Cancellation/Compensation" on page 11.
11
FN6260.2 April 13, 2007
ISL28270, ISL28273, ISL28470
2.4V TO 5V EN
IN+
IN+ IN-
V+ + ISL28270 + V-
EN
an economical resistor divider can be used to set the voltage at the REF terminal without degrading or affecting the CMRR performance. Any voltage applied to the REF terminal will shift VOUT by VREF times the closed loop gain, which is set by resistors RF and RG. See Figure 29. The FB+ pin can also be connected to the other end of resistor, RG. See Figure 30. Keeping the basic concept that the in-amp maintains constant differential voltage across the input terminals and feedback terminals (FB- - FB+) = (IN+ - IN-), the transfer function of Figure 30 can be derived.
2.4V TO 5V EN
IN-
FB+ FB-
VOUT
VCM
RG
RF
IN+
FIGURE 28. GAIN IS SET BY TWO EXTERNAL RESISTORS, RF AND RG
IN-
IN+ INFB+ FB-
V+ + ISL28270 + V-
EN
VOUT
V IN = IN+ - INRF V OUT = 1 + ------- V IN R G
VCM
(EQ. 1)
RS VREF RG
In Figure 28, the FB+ pin and one end of resistor RG are connected to GND. With this configuration, the gain equation (Equation 1) is only true for a positive swing in VIN; negative input swings will be ignored because the output will be at ground.
RF
FIGURE 30. REFERENCE CONNECTION WITH AN AVAILABLE VREF V IN = IN+ - INRS + RF V OUT = 1 + --------------------- + V REF RG RF V OUT = 1 + ------- ( V IN ) + ( V REF ) R G
Reference Connection
Unlike a three op-amp in-amp realization, a finite series resistance seen at the REF terminal does not degrade the high CMRR performance, eliminating the need for an additional external buffer amplifier. Figure 29 uses the FB+ pin to provide a high impedance REF terminal.
2.4V to 5V EN
(EQ. 3)
(EQ. 4)
IN+ IN+ ININ2.9V to 5V VCM R1 REF R2 RG FB+ FB+ -
V+
EN
A finite resistance RS in series with the VREF source, adds an output offset of VIN*(RS/RG). As the series resistance RS approaches zero, Equation 3 is simplified to Equation 4 for Figure 30. VOUT is simply shifted by an amount VREF.
ISL28270 + V-
VOUT
External Resistor Mismatches
Because of the independent pair of feedback terminals provided by the in-amps, the CMRR is not degraded by any resistor mismatches. Hence, unlike a three op-amp and especially a two op-amp in-amp realization, the ISL28270, ISL28273 and ISL28470 reduce the cost of external components by allowing the use of 1% or more tolerance resistors without sacrificing CMRR performance. The CMRR will be typically 110dB regardless of the tolerance of the resistors used. Instead, a resistor mismatch results in a higher deviation from the theoretical gain - gain Error.
RF
FIGURE 29. GAIN SETTING AND REFERENCE CONNECTION
.
V IN = IN+ - INRF RF V OUT = 1 + ------- ( V IN ) + 1 + ------- ( V REF ) R G R G (EQ. 2)
Gain Error and Accuracy
The gain error indicated in the "Electrical Specifications" Table on page 3 is the inherent gain error alone. The gain error specification listed does not include the gain error contributed by the resistors. There is an additional gain error
The FB+ pin is used as a REF terminal to center or to adjust the output. Because the FB+ pin is a high impedance input, 12
FN6260.2 April 13, 2007
ISL28270, ISL28273, ISL28470
due to the tolerance of the resistors used. The resulting non-ideal transfer function effectively becomes Equation 5:
RF V OUT = 1 + ------- x [ 1 ( E RG + E RF + E G ) ] x V IN R G (EQ. 5)
pulled above 2V, and will power up when the EN bar is pulled below 0.8V.
Unused Channels
The ISL28270, ISL28273 and ISL28470 are Dual-channel and Quad-channel op-amps. If the application only requires one channel when using the ISL28270, ISL28273 or less than 4-channels when using the ISL28470, the user must configure the unused channel(s) to prevent them from oscillating. The unused channel(s) will oscillate if the input and output pins are floating. This will result in higher than expected supply currents and possible noise injection into the channel being used. The proper way to prevent this oscillation is to short the output to the negative input and ground the positive input (as shown in Figure 31).
Where:
ERG = Tolerance of RG ERF = Tolerance of RF EG = Gain Error of the ISL28270
The term [1 - (ERG +ERF +EG)] is the deviation from the theoretical gain. Thus, (ERG +ERF +EG) is the total gain error. For example, if 1% resistors are used, the total gain error would be as follows in Equation 6:
TotalGainError = ( E RG + E RF + E G ( typical ) ) TotalGainError = ( 0.01 + 0.01 + 0.005 ) = 2.5% (EQ. 6)
IN+ IN-
+ -
1/2 ISL28270, ISL28273 1/4 ISL28470
Disable/Power-Down
The ISL28270, ISL28273 and ISL28470 have an enable/disable pin for each channel. They can be powered down to reduce the supply current to typically 4A when all channels are off. When disabled, the corresponding output is in a high impedance state. The active low EN pin has an internal pull down and hence can be left floating and the in-amp enabled by default. When the EN is connected to an external logic, the in-amp will shutdown when the EN pin is
FB+ FB-
+ -
RG
RF
FIGURE 31. PREVENTING OSCILLATIONS IN UNUSED CHANNELS
13
FN6260.2 April 13, 2007
ISL28270, ISL28273, ISL28470 Shrink Small Outline Plastic Packages (SSOP) Quarter Size Outline Plastic Packages (QSOP)
N INDEX AREA E -B1 2 3 L SEATING PLANE -AD -CA 0.25 0.010 h x 45 GAUGE PLANE H 0.25(0.010) M BM
M28.15
28 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE (0.150" WIDE BODY) INCHES SYMBOL A A1 A2 B C MIN 0.053 0.004 0.008 0.007 0.386 0.150 MAX 0.069 0.010 0.061 0.012 0.010 0.394 0.157 MILLIMETERS MIN 1.35 0.10 0.20 0.18 9.81 3.81 MAX 1.75 0.25 1.54 0.30 0.25 10.00 3.98 NOTES 9 3 4 5 6 7 8 Rev. 1 6/04
A1 0.10(0.004) A2 C
D E e H h L N
e
B 0.17(0.007) M C AM BS
0.025 BSC 0.228 0.0099 0.016 28 0 8 0.244 0.0196 0.050
0.635 BSC 5.80 0.26 0.41 28 0 6.19 0.49 1.27
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "B" does not include dambar protrusion. Allowable dambar protrusion shall be 0.10mm (0.004 inch) total in excess of "B" dimension at maximum material condition. 10. Controlling dimension: INCHES. Converted millimeter dimensions are not necessarily exact.
14
FN6260.2 April 13, 2007
ISL28270, ISL28273, ISL28470 Quarter Size Outline Plastic Packages Family (QSOP)
A D N (N/2)+1
MDP0040
QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY INCHES SYMBOL QSOP16 QSOP24 QSOP28 TOLERANCE NOTES
PIN #1 I.D. MARK
A A1 A2 b
0.068 0.006 0.056 0.010 0.008 0.193 0.236 0.154 0.025 0.025 0.041 16
0.068 0.006 0.056 0.010 0.008 0.341 0.236 0.154 0.025 0.025 0.041 24
0.068 0.006 0.056 0.010 0.008 0.390 0.236 0.154 0.025 0.025 0.041 28
Max. 0.002 0.004 0.002 0.001 0.004 0.008 0.004 Basic 0.009 Basic Reference
1, 3 2, 3 Rev. F 2/07
E
E1
1 B 0.010 CAB
(N/2)
c D E
e C SEATING PLANE 0.004 C 0.007 CAB b
H
E1 e L L1 N
L1 A c SEE DETAIL "X"
NOTES: 1. Plastic or metal protrusions of 0.006" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994.
0.010 A2 GAUGE PLANE L 44 DETAIL X
A1
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 15
FN6260.2 April 13, 2007

▲Up To Search▲

Price & Availability of ISL28470

	To Download ISL28470 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .